博士（工学）, Tokyo Institute of Technology

Computer system, Computer Architecture

Computer system, Reconfigurable system

Computer system, Custom computing

2009 - 2014, Tokyo Institute of Technology, Graduate School of Information Science and Engineering

2007 - 2009, Tokyo Institute of Technology, Graduate School of Information Science and Engineering

Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs
Jinguji, Akira; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E104D(12), 2040-2047, Dec. 2021

Fast EUV lithography simulation using convolutional neural network
Tanabe, Hiroyoshi; Sato, Shimpei; Takahashi, Atsushi;
JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3, 20(4), 041202, Oct. 2021

Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder
Soga, Naoto; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E104D(8), 1121-1129, Aug. 2021

Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism
Ukon, Yuta; Sato, Shimpei; Takahashi, Atsushi;
IEICE Transactions on Electronics, E104C(7), 309-318, Jul. 2021

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators
Shimoda, Masayuki; Sada, Youki; Kuramochi, Ryosuke; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E103D(12), 2463-2470, Dec. 2020

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections
Sato, Shimpei; Akagi, Kano; Takahashi, Atsushi;
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E103A(9), 1037-1044, Sep. 2020

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution
Sato, Shimpei; Sassa, Eijiro; Ukon, Yuta; Takahashi, Atsushi;
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E102A(12), 1760-1769, Dec. 2019

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA
Shimoda, Masayuki; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E102D(5), 1020-1028, May 2019

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers
Nakahara, Hiroki; Yonekawa, Haruyoshi; Fujii, Tomoya; Shimoda, Masayuki; Sato, Shimpei;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E102D(5), 1003-1011, May 2019

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
Ando, Kota; Ueyoshi, Kodai; Orimo, Kentaro; Yonekawa, Haruyoshi; Sato, Shimpei; Nakahara, Hiroki; Takamaeda-Yamazaki, Shinya; Ikebe, Masayuki; Asai, Tetsuya; Kuroda, Tadahiro; Motomura, Masato;
IEEE Journal of Solid-State Circuits, 53(4), 983-994, Apr. 2018

ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment
Sato, Shimpei; Kobayashi, Ryohei; Kise, Kenji;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E101D(2), 344-353, Feb. 2018

An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design
Jinguji, Akira; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E101D(2), 354-362, Feb. 2018

A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA
Fujii, Tomoya; Sato, Shimpei; Nakahara, Hiroki;
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E101D(2), 376-386, Feb. 2018

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
Van Chu, Thiem; Sato, Shimpei; Kise, Kenji;
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 10(4), Dec. 2017

A Fast LUT Based Point Intensity Computation for OPC Algorithm
Tahsin Shameem, Shimpei Sato, Atsushi Takahashi, Hiroyoshi Tanabe, Yukihide Kohira and Chikaaki Kodama
The 23rd Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2021), 29 Mar. 2021

Fast 3D lithography simulation by convolutional neural network
Hiroyoshi Tanabe, Shimpei Sato and Atsushi Takahashi
SPIE Advanced Lithography, 22 Feb. 2021, Not invited

A Table Look-Up Based Ternary Neural Network Processor
Yuta Suzuki, Naoto Soga, Shimpei Sato and Hiroki Nakahara
The 50th IEEE International Symposium on Multiple-Valued Logic (ISMVL '20), 10 Nov. 2020

Fast 3D lithography simulation by convolutional neural network: POC study
Hiroyoshi Tanabe, Shimpei Sato and Atsushi Takahashi
SPIE Photomask Technology + EUV Lithography 2020, 20 Sep. 2020, Not invited

Fast Monocular Depth Estimation on an FPGA
Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato and Hiroki Nakahara
The 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW '20), 18 May 2020, Not invited

Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAs
Akira Jinguji, Shimpei Sato and Hiroki Nakahara
The 28th International Symposium on Field-Programmable Custom Computing Machines (FCCM '20), 08 Apr. 2020, Not invited

Design Project 1
Shinshu University

Advanced Computer Architecture
Shinshu University

Basical Experiment of Electrical and Computer Engineering
Shinshu University

Programing language 1
Shinshu University

Mar. 2016
IEEE

May 2016
IEICE

May 2006
IPSJ